A timeline of semiconductor process nodes
A process node names a generation of chip manufacturing technology. Smaller node numbers historically meant smaller transistors, but since around 22nm the names are marketing labels for a process generation rather than a measured dimension. This reference lays out the path from 90nm down to 2nm, with the approximate year each entered volume production, the dominant makers, and the transistor structure that defined it.
The real engineering story: structures, not numbers
Each new node packs more transistors into the same area and usually improves speed and power. The big structural shifts matter more than the numbers:
Planar transistors (90nm–28nm): the gate sits flat on top of the silicon channel. As nodes shrank, leakage current became harder to control because the gate could only control the channel from one side. The 28nm node was roughly the last generation where planar achieved good yield at volume production.
FinFET (22nm/16nm – 7nm/5nm): Intel introduced FinFET at 22nm in 2011; TSMC followed at 16nm. A thin vertical fin of silicon rises from the substrate, and the gate wraps three sides. This dramatically improved leakage control and allowed scaling to continue through 5nm, because the additional gate surfaces kept the transistor switching crisply even as dimensions shrank.
Gate-all-around / nanosheet (3nm onward): Samsung introduced GAA at 3nm, with TSMC and Intel following on their respective 2nm-class nodes. Instead of a vertical fin, GAA uses horizontal stacked sheets of silicon, and the gate wraps all four sides. This provides even better electrostatic control than FinFET and allows finer tuning of performance and power by adjusting the sheet width — a feature FinFET cannot offer.
Why node names stopped meaning dimensions
Before about 22nm, the node name was loosely tied to the gate length or half-pitch of key features — 90nm meant something physically close to 90nm. As scaling became harder, engineers found ways to maintain density improvements through new techniques (multi-patterning, new materials) without proportionally shrinking every feature. By 7nm, the naming was entirely disconnected from physical dimensions and became a competitive marketing label: TSMC’s 7nm is denser than some competitors’ “7nm” even though both use the same name.
Intel’s renamed roadmap
Intel historically named its nodes more aggressively than foundries. Its original “10nm” was comparable to TSMC’s “7nm” in density. Rather than continuing with confusing equivalences, Intel renamed its roadmap in 2021:
| Intel name | Approximate foundry equivalent |
|---|---|
| Intel 7 | TSMC N7 class |
| Intel 4 | TSMC N5 class |
| Intel 3 | TSMC N3 class |
| Intel 20A / 18A | 2nm class (ångström generation) |
The “A” in 18A stands for ångström (0.1nm), signalling Intel’s entry into the sub-2nm naming era alongside TSMC’s N2 and Samsung’s SF2.
Tips and notes
- Node names below ~22nm are marketing generations, not physical gate lengths.
- The planar → FinFET → GAA progression is the real engineering story.
- Intel 18A’s “A” means ångström — roughly a 1.8nm-class node.
- Treat the years as volume-production estimates; announcement, tape-out, and full-volume dates often differ by 1–2 years, and sources vary.