PCIe generations and bandwidth
PCI Express is the backbone that connects GPUs, NVMe SSDs, and add-in cards to the CPU. Each generation roughly doubles bandwidth, and links scale further by lane width. This reference lists every generation from PCIe 1.0 to 7.0 with its transfer rate, encoding scheme, and per-lane bandwidth, plus a calculator that multiplies any generation by any lane width.
How it works
PCIe quotes a raw signalling rate in gigatransfers per second (GT/s) per lane. To get usable bandwidth you remove line-encoding overhead. Generations 1 and 2 use 8b/10b encoding (20% overhead): PCIe 2.0 at 5 GT/s yields 500 MB/s per lane. Generations 3 through 5 use the far more efficient 128b/130b encoding (about 1.5% overhead): PCIe 3.0 at 8 GT/s yields about 985 MB/s per lane, and each later generation doubles that.
Total link bandwidth is per-lane bandwidth × lane width. Common widths are x1, x4 (most NVMe drives), x8, and x16 (most graphics cards). PCIe is full-duplex, so each lane carries that bandwidth simultaneously in both directions. Generations 6 and 7 switch from two-level NRZ to four-level PAM4 signalling, packing two bits per symbol, plus FLIT framing with forward error correction to keep errors in check.
Quick-reference: per-lane usable bandwidth by generation
| Generation | GT/s | Encoding | Usable per lane | x4 link | x16 link |
|---|---|---|---|---|---|
| PCIe 1.0 | 2.5 | 8b/10b | ~250 MB/s | ~1 GB/s | ~4 GB/s |
| PCIe 2.0 | 5.0 | 8b/10b | ~500 MB/s | ~2 GB/s | ~8 GB/s |
| PCIe 3.0 | 8.0 | 128b/130b | ~985 MB/s | ~3.94 GB/s | ~15.75 GB/s |
| PCIe 4.0 | 16.0 | 128b/130b | ~1.97 GB/s | ~7.88 GB/s | ~31.5 GB/s |
| PCIe 5.0 | 32.0 | 128b/130b | ~3.94 GB/s | ~15.75 GB/s | ~63 GB/s |
| PCIe 6.0 | 64.0 | PAM4/FLIT | ~7.88 GB/s | ~31.5 GB/s | ~126 GB/s |
| PCIe 7.0 | 128.0 | PAM4/FLIT | ~15.75 GB/s | ~63 GB/s | ~252 GB/s |
These are theoretical maximums before device-controller and bus-transaction overhead.
Tips and notes
- A device negotiates to the lowest common generation and the narrowest common width, so a Gen5 SSD in a Gen3 slot runs at Gen3 speeds.
- Splitting lanes (bifurcation) lets one x16 slot host multiple devices, e.g. four x4 NVMe drives on a single x16 adapter, if the motherboard supports it.
- Higher generations have shorter clean signal reach, so PCIe 5.0 and beyond often need retimers or shorter, higher-quality traces and cables.
- The figures here are theoretical usable maximums; real throughput is also limited by the device controller, thermals, and the host’s available lanes.
Practical context: where each generation matters
NVMe SSDs overwhelmingly use x4 links. Gen3 x4 offers about 3.94 GB/s, which was the bottleneck for fast SSDs until PCIe 4.0 arrived and doubled sequential speeds. Most consumer Gen4 NVMe drives saturate 7 GB/s reads; Gen5 NVMe drives push toward 14 GB/s on capable platforms.
Graphics cards use x16 links. Even PCIe 3.0 x16 at around 15.75 GB/s is rarely the bottleneck for current GPUs — modern discrete graphics cards typically do not saturate a PCIe 4.0 x16 link in real workloads. The GPU compute and memory bandwidth are almost always the limiting factor first.
Add-in capture cards and data-acquisition boards sometimes benefit meaningfully from higher-generation PCIe when streaming large amounts of data continuously. Knowing the actual link generation and width your slot provides helps diagnose whether a device could be throttled by the interface.
Checking your current link: In Windows, Device Manager shows the current Link Speed and Link Width for each PCIe device under its properties. On Linux, lspci -vv shows LnkSta: Speed and Width for each device. Comparing LnkCap (the device maximum) with LnkSta (the negotiated speed) immediately reveals a mismatch.